1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular to a dynamic access memory (DRAM) metal oxide semiconductor field effect transistor (MOSFET) which contains gate oxide regions having various oxide thicknesses that are dependent upon the width of the active device areas. The present invention also provides an improved gate oxidation process useful in fabricating such a DRAM MOSFET structure wherein the gate oxide thickness is determined by the channel width of the MOSFET structure.
2. Background of the Invention
In current dynamic access memory (DRAM) technologies, the threshold voltage of the device does not scale with the power supply voltage and ground rules because of the non-scalability of the sub-threshold slope. Thus, the minimum gate oxide thickness and/or maximum wordline boost voltage of the array MOSFET is constrained by reliability considerations.
When used for the support MOSFET, the relatively thick gate oxide (having a thickness of greater than ≈6 nm for 0.175 xcexcm technology) required by the array MOSFET results in degradation in the performance of the MOSFET device. Furthermore, if a thinner gate oxide is used to improve the performance of the support circuitry, charge transfer efficiency in the device array is compromised as a result of the reliability limitation of the wordline boost voltage.
Ideally, in such technology, a dual gate oxide thickness is desired. In the prior art, it is known to subject the DRAM array transistor to a dual gate oxidation process or an alternative gate oxidation process as compared to the support circuitry. These additional gate oxidation processing steps are costly, and they are also yield limiting since one must utilize additional processing steps such as but not limited to: masking, exposure, etching, oxidizing and strip masking, which either grow a second oxide or mask an existing oxide introducing defect sources into the entire structure of the MOSFET device. As such, prior art gate oxidation processes are not reliable nor cost efficient.
In view of the drawbacks mentioned with prior art processes of fabricating DRAM MOSFETs having dual gate oxide thicknesses, a new and improved method of producing such devices using a single gate oxidation step would be beneficial in the semiconductor industry.
One object of the present invention is to provide a dual gate oxidation process for use in DRAM technologies having feature sizes of about 0.15 xcexcm or less which does not impose the additional manufacturing steps or costs required by prior gate oxidation processes.
Another object of the present invention is to provide a dual gate oxidation process which provides a path for growing a thicker gate oxide on the DRAM transistor relative to the support transistor allowing for increased gate voltage, reduced vertical electrical field and improved corner reliability to electric field.
A still further object of the present invention is to design a DRAM MOSFET having a minimum ground rule width, to maximize density.
An additional object of the present invention is to provide thicker gate oxide MOSFETs having high current capability suitable for reliable I/O devices capable of interfacing with circuitry external to a semiconductor chip operating at voltages which are higher than on the chip.
These and other objects and advantages are met by utilizing the dual gate oxidation method of the present invention wherein the thickness of the gate oxide is determined, i.e. controlled, by the width of the channel the MOSFET; narrow width devices having a gate oxide thickness which is greater than those for wide devices. Additionally, the differential in gate oxide thickness may be enhanced in the present invention by decreasing the radius of curvature (increasing sharpness) of the silicon corners.
One aspect of the present invention relates to an integrated circuit, i.e. DRAM MOSFET, which comprises a semiconductor substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions, said plurality of device regions each having opposing edges abutting its corresponding STI region;
selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and
selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
In regard to the object mentioned above concerning thicker gate oxide MOSFETs having high current capabilities, this object is met by providing a plurality of parallel arrayed nested mesa MOSFETs having a narrow width, wherein each narrow MOSFET has a gate oxide which is thicker than the gate oxide of MOSFETs having a mesa with a wider width.
Another aspect of the present invention relates to a dual gate oxidation process which can be used in fabricating the above described integrated circuit. Specifically, the dual gate oxidation process of the present invention comprises the steps of:
(a) forming an oxide pad on a surface of a semiconductor substrate or wafer;
(b) depositing a polish stop layer on top of said oxide pad;
(c) patterning said polish stop layer and oxide pad in predetermined areas wherein active device regions will be formed and developing said pattern:
(d) forming shallow trenches into said semiconductor substrate or wafer;
(e) forming a thermal oxide lining said shallow trenches;
(f) forming a chemical vapor deposited oxide on top of said thermal oxide liner;
(g) planarizing the structure to said polish stop layer;
(h) stripping said polish stop layer and said oxide pad;
(i) forming a sacrificial oxide on the stripped surface under conditions sufficient to produce a predetermined radius of curvature on said semiconductor substrate or wafer;
(j) implanting well regions in said semiconductor substrate or wafer;
(k) stripping said sacrificial oxide; and
(l) forming a gate oxide by oxidation, wherein said oxidation is carried out under conditions which are capable of (I) controlling mechanical stresses formed during said oxidation, (II) forming a flowable oxide at corners of active device regions; and (III) forming a gradient in the oxide thickness extending from corners of active device regions to a middle region thereof.
It should be noted that the conditions employed during the gate oxidation step are carefully selected so as to allow flow of the oxide material away from the corners of the device regions. This step, as well as the small feature sizes and radius of curvature of the structure, allows one to obtain the above structure wherein a thicker gate oxide is grown on a narrower portion of the device structure and a thinner gate oxide is grown on the wider portions of the device structure. Such dual oxide gate thicknesses cannot be obtained by prior art processes utilizing a single gate oxidation step.